Class | Description |
---|---|
ABCD |
The ABCD instruction in all of its variants.
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ADDI |
The ADDI instruction in all of its variants.
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ADDXmem |
The ADDX instruction (mem to mem) in all of its variants.
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ADDXreg |
The ADDX instruction (register to register) in all of its variants.
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ANDI |
The ANDI instruction in all of its variants.
|
ANDI_CCR |
The ANDI_TO_CCR instruction in all of its variants.
|
ANDI_SR |
The ANDI_TO_SR instruction in all of its variants.
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ANDmem |
The AND instruction where the destination is a mem location, in all of its variants.
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ANDreg |
The AND instruction where the destination is a register, in all of its variants.
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Bcc |
The Bcc instructions, excluding BRA, BSR.
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BCHGimm |
The BCHG instruction where the bit number is contained in a word following the instruction, in all of its variants.
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BCHGreg |
The BCHG instruction where the bit number is contained in a register, in all of its variants.
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BCLRimm |
The BCLR instruction where the bit number is contained in a word following the instruction, in all of its variants.
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BCLRreg |
The BCLR instruction where the bit number is contained in a register, in all of its variants.
|
BRA |
The BRA instruction in all of its variants.
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BSETimm |
The BSET instruction where the bit number is contained in a word following the instruction, in all of its variants.
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BSETreg |
The BSET instruction where the bit number is contained in a register, in all of its variants.
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BSR |
The emulated BSR instruction in all of its variants.
|
CHK |
The CHK instruction in all of its variants.
0100ddd110mmmrrr = 4180
where rrr = eareg
mmm = mode
|
DBcc |
A replacement DBcc instruction in all of its variants
This is based on Tony Headford's work.
|
DIVSW |
The emulated DIVS (word sized) instruction in all of its variants.
|
DIVUW |
The emulated DIVU (word sized) instruction in all of its variants.
|
EOR |
The EOR instruction where the destination is a mem location, in all of its variants.
|
EORI |
The EORI instruction in all of its variants.
|
EORI_CCR |
The EORI_TO_CCR instruction in all of its variants.
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EORI_SR |
The EORI_TO_SR instruction in all of its variants.
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EXG |
The EXG instruction in all of its variants.
1100ddd1ooooosss =0xc100
where ddd = dest reg
rrr = src reg
ooooo = opmode 01000 = exchange data regs
01001 = exchange addr regs
10001 = xchange addr and data regs, the data reg is the dest reg
|
EXT |
The EXT instruction in all of its variants.
|
ILLEGAL |
The ILLEGAL instruction in all of its variants.
|
ILLEGALQmon |
Illegal instruction used by Qmon (4afb) - set the correct pc address.
|
LINK |
The LINK instruction in all of its variants.
|
MOVE_FROM_CCR |
The MOVE_FROM_SR instruction in all of its variants.
01000000011mmmrrr = 40c0
where rrr = eareg
mmm = mode
|
MOVE_FROM_SR |
The MOVE_FROM_SR instruction in all of its variants.
01000000011mmmrrr = 40c0
where rrr = eareg
mmm = mode
|
MOVE_TO_CCR |
The MOVE_TO_CCR instruction in all of its variants.
0100010011mmmrrr = 44c0
where rrr = eareg
mmm = mode
|
MOVE_TO_SR |
The MOVE_TO_SR instruction in all of its variants.
0100011011mmmrrr = 46c0
where rrr = eareg
mmm = mode
|
MOVE_USP |
A redefinition of the MOVE TO/FROM USP instructions.
|
MOVEPm2r |
The MOVEPr2m instruction where move is made from mem to reg.
|
MOVEPr2m |
The MOVEPr2m instruction where move is made from reg to mem.
|
MOVEQ |
A replacement MOVEQ instruction in all of its variants
This is based on Tony Headford's work.
|
MULSW |
The emulated MULS (word sized) instruction in all of its variants.
|
MULUW |
The emulated MULU (word sized) instruction in all of its variants.
|
NBCD |
The NBCD instruction in all of its variants.
|
NEG |
The NEG instruction in all of its variants.
01000100ssmmmrrr = 4400
where rrr = data reg to be swapped
|
NEGX |
The NEGX instruction in all of its variants.
4000
|
NOP |
The NOP instruction.
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NOT |
The NOT instruction in all of its variants.
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NULL |
This is a "null" instruction - actually means that an illegal opcode will be "executed".
|
ORI |
The ORI instruction in all of its variants.
|
ORI_CCR |
The ORI_TO_CCR instruction in all of its variants.
|
ORI_SR |
The ORI_TO_SR instruction in all of its variants.
|
ORmem |
The OR instruction where the destination is a mem location, in all of its variants.
|
ORreg |
The OR instruction where the destination is a register, in all of its variants.
|
PEA |
The PEA instruction in all of its variants.
0100100001mmmrrr =0x4840
where rrr = src reg
mmm = mod
|
RESET |
The RESET instructions.
|
RTE |
A redefinition of the RTE instruction.
|
RTR |
A redefinition of the RTR instruction.
|
RTS |
A definition of the RTS instruction.
|
SBCD |
The ABCD instruction in all of its variants.
|
SCC |
The SCC instruction in all of its variants.
0101cccc11mmmrrr = 50c0
where rrr = data reg to be swapped
mmm = mode
cccc= condition
|
STOP |
The STOP instructions.
|
SUBI |
The SUBI instruction in all of its variants.
|
SUBXmem |
The SUBX instruction (mem to mem) in all of its variants.
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SUBXreg |
The SUBX instruction (mem to mem) in all of its variants.
|
SWAP |
The SWAP instruction in all of its variants.
0100100001000rrr =0x4840
where rrr = data reg to be swapped
|
TAS |
The TAS instruction in all of its variants.
0100101011mmmrrr = 4ac0
where rrr = eareg
mmm = mode
|
TEST |
Illegal instruction used by Qmon (4afb) - set the correct pc address.
|
TRAP |
The TRAP instruction in all of its variants.
|
TRAPV |
The TRAPV instruction in all of its variants.
|
UNLK |
The UNLK instruction in all of its variants.
|